Current-mode logic (CML) slicers, which quantify analog input signals into digital output bits, have been widely adopted in receivers (e.g., serial/deserializer (SerDes) receivers). The CML slicer has two phases of operation: a tracking phase during which the CML slicer tracks the input signal (e.g., analog signal waveform) for a first half of a clock cycle, and a regeneration phase during which the CML slicer regenerates the analog input as a digital output during a second half of the clock cycle.
The operational demands placed on conventional CML slicers often result in conflicting requirements. For example, low tracking latency (i.e., high tracking bandwidth) is desired because it reduces the circuit-induced inter-symbol-interface (ISI), which is additive to channel induced ISI, and because lower tracking latency serves to close the timing paths where decision feedback equalization (DFE) is applied. To achieve low tracking latency, the load resistor needs to be sufficiently small. On the other hand, high regeneration gain is also desired so that the output of the CML slicer may be a wide-swing digital signal, which is more immune to noise and other non-ideality than an analog signal. To achieve high regeneration gain, the load resistor needs to be sufficiently large. Therefore, a trade-off exists between the tracking latency and the regeneration gain in conventional slicer designs.
Conventional solutions attempt to reach a compromise between the two requirements by selecting an output resistance that is small enough to satisfy a minimum tracking latency requirement, and is large enough to satisfy a minimum regeneration gain requirement. This, however, leads to sub-optimal design.
The above information disclosed in this Background section is only for enhancement of understanding of the invention, and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.